PIC16F74T-E/L【PDF 76/104 页】IC MCU FLASH 4KX14 A/D 44PLCC

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Sheet目录3890

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Micrel, Inc.

KSZ8851-16MLLJ

March 2010

M9999-030210-1.0

Interrupt Status Register (0x92 – 0x93): ISR (Continued)

Bit

Default Value

R/W

Description

0x0

RXWFDIS Receive Wakeup Frame Detect Interrupt Status

When this bit is set, it indicates that Receive wakeup frame detect status has occurred.

Write “1000” to PMECR[5:2] to clear this bit

0x0

RXMPDIS Receive Magic Packet Detect Interrupt Status

When this bit is set, it indicates that Receive magic packet detect status has occurred.

Write “0100” to PMECR[5:2] to clear this bit.

0x0

LDIS Linkup Detect Interrupt Status

When this bit is set, it indicates that wake-up from linkup detect status has occurred. Write

“0010” to PMECR[5:2] to clear this bit.

0x0

EDIS Energy Detect Interrupt Status

When this bit is set and bit 2=1, bit 0=0 in IER register, it indicates that wake-up from

energy detect status has occurred. When this bit is set and bit 2, 0=1 in IER register, it

indicates that wake-up from delay energy detect status has occurred.

Write “0001” to PMECR[5:2] to clear this bit.

0x0

Reserved.

0x0

Reserved

0x94 – 0x9B: Reserved

RX Frame Count & Threshold Register (0x9C – 0x9D): RXFCTR

This register indicates the current total amount of received frame count in RXQ frame buffer and also is used to program

the received frame count threshold.

Bit

Default Value

R/W

Description

15-8

0x00

RXFC RX Frame Count

To indicate the total received frames in RXQ frame buffer when receive interrupt (bit13=1 in

ISR) occurred and write “1” to clear this bit 13 in ISR. The host CPU can start to read the

updated receive frame header information in RXFHSR/RXFHBCR registers after read this

RX frame count register.

7-0

0x00

RXFCT Receive Frame Count Threshold

To program received frame count threshold value.

When bit 5 set to 1 in RXQCR register, the KSZ8851-16MLLJ will set RX interrupt (bit 13 in

ISR) when the number of received frames in RXQ buffer exceeds the threshold set in this

TX Next Total Frames Size Register (0x9E – 0x9F): TXNTFSR

This register is used by the host CPU to program the total amount of TXQ buffer space requested for the next transmit.

Bit

Default Value

R/W

Description

15-0

0x0000

TXNTFS TX Next Total Frames Size

The host CPU is used to program the total amount of TXQ buffer space which is required

for next total transmit frames size in double-word count.

When bit 1 (TXQ memory available monitor) is set to 1 in TXQCR register, the KSZ8851-

16MLLJ will generate interrupt (bit 6 in ISR register) to CPU when TXQ memory is

available based upon the total amount of TXQ space requested by CPU at this register.

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